Instruments for getting runtime information about the target system architecture. More...

#include "chsvbase.h"
#include "chsvsal.h"

Namespaces
	Chusov
	Basic chsvlib namespace.

Macros
#define	X86_MMX_ID 0x0000000000000001llu
	A bit mask used to request support of the Intel MMX instruction set. More...

#define	X86_SSE_ID 0x0000000000000002llu
	A bit mask used to request support of the Intel SSE instruction set. More...

#define	X86_SSE2_ID 0x0000000000000004llu
	A bit mask used to request support of the Intel SSE2 instruction set. More...

#define	X86_SSE3_ID 0x0000000000000008llu
	A bit mask used to request support of the Intel SSE3 instruction set. More...

#define	X86_SSSE3_ID 0x0000000000000010llu
	A bit mask used to request support of the Intel SSSE3 instruction set. More...

#define	X86_SSE4_1_ID 0x0000000000000038llu
	A bit mask used to request support of the Intel SSE4.1 instruction set. More...

#define	X86_SSE4_2_ID 0x0000000000000070llu
	A bit mask used to request support of the Intel SSE4.2 instruction set. More...

#define	X86_CRC32_ID 0x0000000000000040llu
	A bit mask used to request support of the Intel CRC32 instruction. More...

#define	X86_MOVBE_ID 0x0000000000000080llu
	A bit mask used to request support of the Intel MOVBE instruction. More...

#define	X86_POPCNT_ID 0x0000000000000140llu
	A bit mask used to request support of the Intel POPCNT instruction. More...

#define	X86_AESNI_ID 0x0000000000000206llu
	A bit mask used to request support of the Intel AESNI instructions. More...

#define	X86_CLMUL_ID 0x0000000000000406llu
	A bit mask used to request support of the Intel CLMUL instruction set. More...

#define	X86_OSXSAVE_ID 0x0000000000000800llu
	A bit mask used to request support of the Intel XSAVE instructions from the CPU and the OS. More...

#define	X86_AVX_ID 0x0000000000001000llu
	A bit mask used to request support of the Intel AVX instruction set. More...

#define	X86_FMA_ID 0x0000000000003000llu
	A bit mask used to request support of the Intel FMA instruction set. More...

#define	X86_VAES_ID 0x0000000000004000llu
	A bit mask used to request support of the Intel VAES instructions. More...

#define	X86_AVX2_ID 0x0000000000009000llu
	A bit mask used to request support of the Intel AVX2 instruction set. More...

#define	X86_AVX512F_ID 0x0000000000010000llu
	A bit mask used to request support of the Intel AVX512F instruction set. More...

#define	X86_AVX512DQ_ID 0x0000000000030000llu
	A bit mask used to request support of the Intel AVX512DQ instruction set. More...

#define	X86_AVX512_IFMA_ID 0x0000000000050000llu
	A bit mask used to request support of the Intel AVX512_IFMA instruction set. More...

#define	X86_AVX512PF_ID 0x0000000000090000llu
	A bit mask used to request support of the Intel AVX512PF instruction set. More...

#define	X86_AVX512ER_ID 0x0000000000110000llu
	A bit mask used to request support of the Intel AVX512ER instruction set. More...

#define	X86_AVX512CD_ID 0x0000000000210000llu
	A bit mask used to request support of the Intel AVX512CD instruction set. More...

#define	X86_AVX512BW_ID 0x0000000000410000llu
	A bit mask used to request support of the Intel AVX512BW instruction set. More...

#define	X86_AVX512VL_F_ID 0x0000000000810000llu
	A bit mask used to request support of the Intel AVX512VL+AVX512F instruction set. More...

#define	X86_AVX512VL_CD_ID 0x0000000000A10000llu
	A bit mask used to request support of the Intel AVX512VL+AVX512CD instruction set. More...

#define	X86_AVX512VL_DQ_ID 0x0000000000830000llu
	A bit mask used to request support of the Intel AVX512VL+AVX512DQ instruction set. More...

#define	X86_AVX512VL_BW_ID 0x0000000000C10000llu
	A bit mask used to request support of the Intel AVX512VL+AVX512BW instruction set. More...

#define	X86_AVX512_VBMI_ID 0x0000000001000000llu
	A bit mask used to request support of the Intel VBMI instruction set. More...

#define	X86_AVX512_VBMI2_ID 0x0000000002000000llu
	A bit mask used to request support of the Intel VBMI2 instruction set. More...

#define	X86_AVX512_VNNI_ID 0x0000000004000000llu
	A bit mask used to request support of the Intel AVX512_VNNI instruction set. More...

#define	X86_AVX_VNNI_ID X86_AVX512_VNNI_ID
	A bit mask used to request support of the Intel AVX_VNNI instruction set. More...

#define	X86_VPCLMULQDQ_ID 0x0000000008000000llu
	A bit mask used to request support of the Intel VPCLMULQDQ instruction. More...

#define	X86_AVX512_BITALG_ID 0x0000000010000000llu
	A bit mask used to request support of the Intel AVX512_BITALG instruction set. More...

#define	X86_AVX512_VPOPCNTDQ_ID 0x0000000020000000llu
	A bit mask used to request support of the Intel AVX512_VPOPCNTD instruction. More...

#define	X86_AVX512_VP2INTERSECT_ID 0x0000000040000000llu
	A bit mask used to request support of the Intel AVX512_VPOPCNTD instruction. More...

#define	X86_SHA_ID 0x0000000080000000llu
	A bit mask used to request support of the Intel SHA instruction set. More...

#define	X86_BMI1_ID 0x0000000100000000llu
	A bit mask used to request support of the Intel BMI1 instruction set. More...

#define	X86_BMI2_ID 0x0000000200000000llu
	A bit mask used to request support of the Intel BMI2 instruction set. More...

#define	X86_LZCNT_ID 0x0000000400000000llu
	A bit mask used to request support of the Intel LZCNT instruction. To check availability of TZCNT, use the ... mask. More...

#define	X86_RDTSCP_ID 0x0000000800000000llu
	A bit mask used to request support of the Intel RDTSCP instruction. More...

#define	x86_cpuid_test_feature(feature_id) implementation
	DOXYGEN. More...

#define	x86_cpuid_max_basic_level() implementation
	Returns a maximum input value for basic CPUID information about the active x86 or x86-64 CPU, or a compile-time zero if the target architecture is neither of those two.

#define	x86_cpuid_max_extended_level() implementation
	Returns a maximum input value for extended function CPUID information about the active x86 or x86-64 CPU, or a compile-time zero if the target architecture is neither of those two.

#define	get_xcr0() implementation
	Returns the lower 32 bits of the XCR0 register, or zero if the target architecture is neither x86 nor x86-64. More...

#define	MMX_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_MMX_ID)

#define	MMX_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_MMX_ID))
	Checks whether the current central processor supports Intel MMX.

#define	SSE_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSE_ID)

#define	SSE_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSE_ID))
	Checks whether the current central processor supports Intel SSE.

#define	SSE2_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSE2_ID)

#define	SSE2_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSE2_ID))
	Checks whether the current central processor supports Intel SSE2.

#define	SSE3_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSE3_ID)

#define	SSE3_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSE3_ID))
	Checks whether the current central processor supports Intel SSE3.

#define	SSSE3_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSSE3_ID)

#define	SSSE3_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSSE3_ID))
	Checks whether the current central processor supports Intel SSSE3.

#define	SSE4_1_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSE4_1_ID)

#define	SSE4_1_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSE4_1_ID))
	Checks whether the current central processor supports Intel SSE4.1.

#define	SSE4_2_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SSE4_2_ID)

#define	SSE4_2_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_SSE4_2_ID))
	Checks whether the current central processor supports Intel SSE4.2.

#define	CRC32_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_CRC32_ID)

#define	CRC32_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_CRC32_ID))
	Checks whether the current central processor supports Intel AESNI instructions.

#define	MOVBE_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_MOVBE_ID)

#define	MOVBE_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_MOVBE_ID))
	Checks whether the current central processor supports Intel MOVBE instruction.

#define	POPCNT_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_POPCNT_ID)

#define	POPCNT_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_POPCNT_ID))
	Checks whether the current central processor supports Intel MOVBE instruction.

#define	AESNI_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AESNI_ID)

#define	AESNI_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_AESNI_ID))
	Checks whether the current central processor supports Intel AESNI instructions.

#define	OSXSAVE_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_FMA_ID)

#define	OSXSAVE_SUPPORTED() (((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_OSXSAVE_ID))
	Checks whether the current central processor supports Intel OSXSAVE.

#define	FMA_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_FMA_ID)

#define	FMA_SUPPORTED() (((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_FMA_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE)))
	Checks whether the current central processor supports Intel FMA.

#define	CLMUL_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_CLMUL_ID)

#define	CLMUL_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_CLMUL_ID))
	Checks whether the current central processor supports Intel CLMUL.

#define	AVX_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX_ID)

#define	AVX_SUPPORTED() ((x86_cpuid_max_basic_level() >= 1) && x86_cpuid_test_feature(X86_AVX_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE))
	Checks whether the current central processor supports Intel AVX.

#define	AVX2_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX2_ID)

#define	AVX2_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX2_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE))
	Checks whether the current central processor supports Intel AVX-2.

#define	AVX512F_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512F_ID)

#define	AVX512F_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512F_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512F.

#define	AVX512PF_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512PF_ID)

#define	AVX512PF_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512PF_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512PF.

#define	AVX512ER_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512ER_ID)

#define	AVX512ER_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512ER_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512ER.

#define	AVX512CD_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512CD_ID)

#define	AVX512CD_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512CD_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512CD.

#define	AVX512DQ_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512DQ_ID)

#define	AVX512DQ_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512DQ_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512DQ.

#define	AVX512BW_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512BW_ID)

#define	AVX512BW_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512BW_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512BW.

#define	AVX512VL_F_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512VL_F_ID)

#define	AVX512VL_F_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512VL_F_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512VL extensions for AVX-512F instructions.

#define	AVX512VL_CD_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512VL_CD_ID)

#define	AVX512VL_CD_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512VL_CD_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512VL extensions for AVX-512CD instructions.

#define	AVX512VL_DQ_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512VL_DQ_ID)

#define	AVX512VL_DQ_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512VL_DQ_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512VL extensions for AVX-512DQ instructions.

#define	AVX512VL_BW_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512VL_BW_ID)

#define	AVX512VL_BW_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512VL_BW_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX-512VL extensions for AVX-512BW instructions.

#define	AVX512_IFMA_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_IFMA_ID)

#define	AVX512_IFMA_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_IFMA_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_IFMA instructions.

#define	AVX512_VNNI_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_VNNI_ID)

#define	AVX512_VNNI_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_VNNI_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_VNNI.

#define	AVX_VNNI_SUPPORTED_MASK(mask) AVX512_VNNI_SUPPORTED_MASK(mask, X86_AVX512_VNNI_ID)

#define	AVX_VNNI_SUPPORTED() AVX512_VNNI_SUPPORTED()
	Checks whether the current central processor supports Intel AVX512_VNNI.

#define	SHA_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_SHA_ID)

#define	SHA_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_SHA_ID))
	Checks whether the current central processor supports Intel SHA.

#define	VAES_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_VAES_ID)

#define	VAES_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_VAES_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel VAES instructions.

#define	VPCLMULQDQ_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_VPCLMULQDQ_ID)

#define	VPCLMULQDQ_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_VPCLMULQDQ_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel VPCLMULQDQ instruction.

#define	BMI1_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_BMI1_ID)

#define	BMI1_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_BMI1_ID))
	Checks whether the current central processor supports Intel BMI1 instructions.

#define	BMI2_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_BMI2_ID)

#define	BMI2_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_BMI2_ID))
	Checks whether the current central processor supports Intel BMI2 instructions.

#define	AVX512_VBMI_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_VBMI_ID)

#define	AVX512_VBMI_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_VBMI_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_VBMI instructions.

#define	AVX512_VBMI2_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_VBMI2_ID)

#define	AVX512_VBMI2_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_VBMI2_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_VBMI2 instructions.

#define	LZCNT_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_LZCNT_ID)

#define	LZCNT_SUPPORTED() ((x86_cpuid_max_extended_level() >= 0x80000001u) && x86_cpuid_test_feature(X86_LZCNT_ID))
	Checks whether the current central processor supports Intel LZCNT instruction.

#define	AVX512_BITALG_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_BITALG_ID)

#define	AVX512_BITALG_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_BITALG_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_BITALG.

#define	AVX512_VPOPCNTDQ_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_VPOPCNTDQ_ID)

#define	AVX512_VPOPCNTDQ_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_VPOPCNTDQ_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512VPOPCNTDQ.

#define	AVX512_VP2INTERSECT_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_AVX512_VP2INTERSECT_ID)

#define	AVX512_VP2INTERSECT_SUPPORTED() ((x86_cpuid_max_basic_level() >= 7) && x86_cpuid_test_feature(X86_AVX512_VP2INTERSECT_ID \| X86_OSXSAVE_ID) && CHECKMASKFLAG(get_xcr0(), X86_XCR0_SSE_STATE \| X86_XCR0_AVX_STATE \| X86_XCR0_AVX512_STATE))
	Checks whether the current central processor supports Intel AVX512_VP2INTERSECT instructions.

#define	RDTSCP_SUPPORTED_MASK(mask) CHECKMASKFLAG(mask, X86_RDTSCP_ID)

#define	RDTSCP_SUPPORTED() ((x86_cpuid_max_extended_level() >= 0x80000001u) && x86_cpuid_test_feature(X86_RDTSCP_ID))
	Checks whether the current central processor supports Intel RDTSCP instruction.

Functions
unsigned long long	get_x86_cpu_info () noexcept
	Returns a bit mask indicating a support by the current processor of various Intel x86 and Intel x86-64 CPU extensions. More...

Detailed Description

Instruments for getting runtime information about the target system architecture.

Returns a bit mask indicating a support by the current processor of various Intel x86 and Intel x86-64 CPU extensions.

Returns: The bit mask corresponding to CPU technologies supported by the current central processor.

The following macro constants define CPU features that can be tested on the target processor using x86_cpuid_max_basic_level(), x86_cpuid_max_extended_level(), x86_cpuid_test_feature() and get_x86_cpu_info() functions.

Technology	Mask value	Mask macro	Helper macros
MMX	0x0000000000000001	X86_MMX_ID	MMX_SUPPORTED_MASK & MMX_SUPPORTED
SSE	0x0000000000000002	X86_SSE_ID	SSE_SUPPORTED_MASK & SSE_SUPPORTED
SSE2	0x0000000000000004	X86_SSE2_ID	SSE2_SUPPORTED_MASK & SSE2_SUPPORTED
SSE3	0x0000000000000008	X86_SSE3_ID	SSE3_SUPPORTED_MASK & SSE3_SUPPORTED
SSSE3	0x0000000000000010	X86_SSSE3_ID	SSSE3_SUPPORTED_MASK & SSSE3_SUPPORTED
SSE4.1	0x0000000000000038	X86_SSE4_1_ID	SSE4_1_SUPPORTED_MASK & SSE4_1_SUPPORTED
SSE4.2	0x0000000000000070	X86_SSE4_2_ID	SSE4_2_SUPPORTED_MASK & SSE4_2_SUPPORTED
CRC32	0x0000000000000040	X86_CRC32_ID	CRC32_SUPPORTED_MASK & CRC32_SUPPORTED
MOVBE	0x0000000000000080	X86_MOVBE_ID	MOVBE_SUPPORTED_MASK & MOVBE_SUPPORTED
POPCNT	0x0000000000000140	X86_POPCNT_ID	POPCNT_SUPPORTED_MASK & POPCNT_SUPPORTED
AESNI	0x0000000000000206	X86_AESNI_ID	AESNI_SUPPORTED_MASK & AESNI_SUPPORTED
CLMUL	0x0000000000000406	X86_CLMUL_ID	CLMUL_SUPPORTED_MASK & CLMUL_SUPPORTED
OSXSAVE	0x0000000000000800	X86_OSXSAVE_ID	OSXSAVE_SUPPORTED_MASK & OSXSAVE_SUPPORTED
AVX	0x0000000000001000	X86_AVX_ID	AVX_SUPPORTED_MASK & AVX_SUPPORTED
FMA	0x0000000000003000	X86_FMA_ID	FMA_SUPPORTED_MASK & FMA_SUPPORTED
VAES	0x0000000000004000	X86_VAES_ID	VAES_SUPPORTED_MASK & VAES_SUPPORTED
AVX2	0x0000000000009000	X86_AVX2_ID	AVX2_SUPPORTED_MASK & AVX2_SUPPORTED
AVX512F	0x0000000000010000	X86_AVX512F_ID	AVX512F_SUPPORTED_MASK & AVX512F_SUPPORTED
AVX512DQ	0x0000000000030000	X86_AVX512DQ_ID	AVX512DQ_SUPPORTED_MASK & AVX512DQ_SUPPORTED
AVX512_IFMA	0x0000000000050000	X86_AVX512_IFMA_ID	AVX512_IFMA_SUPPORTED_MASK & AVX512_IFMA_SUPPORTED
AVX512PF	0x0000000000090000	X86_AVX512PF_ID	AVX512PF_SUPPORTED_MASK & AVX512PF_SUPPORTED
AVX512ER	0x0000000000110000	X86_AVX512ER_ID	AVX512ER_SUPPORTED_MASK & AVX512ER_SUPPORTED
AVX512CD	0x0000000000210000	X86_AVX512CD_ID	AVX512CD_SUPPORTED_MASK & AVX512CD_SUPPORTED
AVX512BW	0x0000000000410000	X86_AVX512BW_ID	AVX512BW_SUPPORTED_MASK & AVX512BW_SUPPORTED
AVX512VL_F	0x0000000000810000	X86_AVX512VL_F_ID	AVX512VL_F_SUPPORTED_MASK & AVX512VL_F_SUPPORTED
AVX512VL_CD	0x0000000000A10000	X86_AVX512VL_CD_ID	AVX512VL_CD_SUPPORTED_MASK & AVX512VL_CD_SUPPORTED
AVX512VL_DQ	0x0000000000830000	X86_AVX512VL_DQ_ID	AVX512VL_DQ_SUPPORTED_MASK & AVX512VL_DQ_SUPPORTED
AVX512VL_BW	0x0000000000C10000	X86_AVX512VL_BW_ID	AVX512VL_BW_SUPPORTED_MASK & AVX512VL_BW_SUPPORTED
AVX512_VBMI	0x0000000001000000	X86_AVX512_VBMI_ID	AVX512_VBMI_SUPPORTED_MASK & AVX512_VBMI_SUPPORTED
AVX512_VBMI2	0x0000000002000000	X86_AVX512_VBMI2_ID	AVX512_VBMI2_SUPPORTED_MASK & AVX512_VBMI2_SUPPORTED
AVX512_VNNI	0x0000000004000000	X86_AVX512_VNNI_ID	AVX512_VNNI_SUPPORTED_MASK & AVX512_VNNI_SUPPORTED
AVX_VNNI¹	0x0000000004000000	X86_AVX_VNNI_ID	AVX_VNNI_SUPPORTED_MASK & AVX_VNNI_SUPPORTED.
VPCLMULQDQ	0x0000000008000000	X86_VPCLMULQDQ_ID	VPCLMULQDQ_SUPPORTED_MASK & VPCLMULQDQ_SUPPORTED
AVX512_BITALG	0x0000000010000000	X86_AVX512_BITALG_ID	AVX512_BITALG_SUPPORTED_MASK & AVX512_BITALG_SUPPORTED
AVX512_VPOPCNTDQ	0x0000000020000000	X86_AVX512_VPOPCNTDQ_ID	AVX512_VPOPCNTDQ_SUPPORTED_MASK & AVX512_VPOPCNTDQ_SUPPORTED
AVX512_VP2INTERSECT	0x0000000040000000	X86_AVX512_VP2INTERSECT_ID	AVX512_VP2INTERSECT_SUPPORTED_MASK & AVX512_VP2INTERSECT_SUPPORTED
SHA	0x0000000080000000	X86_SHA_ID	SHA_SUPPORTED_MASK & SHA_SUPPORTED
BMI1	0x0000000100000000	X86_BMI1_ID	BMI1_SUPPORTED_MASK & BMI1_SUPPORTED
BMI2	0x0000000200000000	X86_BMI2_ID	BMI2_SUPPORTED_MASK & BMI2_SUPPORTED
LZCNT	0x0000000400000000	X86_LZCNT_ID	LZCNT_SUPPORTED_MASK & LZCNT_SUPPORTED
RDTSCP	0x0000000800000000	X86_RDTSCP_ID	RDTSCP_SUPPORTED_MASK & RDTSCP_SUPPORTED

¹X86_AVX_VNNI_ID is equivalent to X86_AVX512_VNNI_ID.

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